1 block diagram features ? ? f max < 1.5ghz ? ? 10 pairs of diferential lvpecl outputs ? ? low additive jitter, < 0.03ps (typ) ? ? selectable diferential input pairs with single ended input option ? ? input clk accepts: lvpecl, lvds, cml, sstl input level ? ? output skew: 40ps (typ) ? ? operating temperature: -40 o c to 85 o c ? ? core power supply: 2.5v 5% & 3.3v 10%, output power supply: 2.5v 5% & 3.3v 10% ? ? packaging (pb-free & green): ? ? 32-pin qfn and tqfp available description te pi6c4911510 is a high-performance low-skew 1-to-10 lvpecl fanout bufer. te pi6c4911510 features two selectable dif - ferential clock inputs and translates to ten lvpecl outputs. te clk inputs accept lvpecl, lvds, cml and sstl signals. pi6c4911510 is ideal for clock distribution applications such as providing fanout for low noise saronix-ecera oscillators. pin confguration v ddo /q2 q2 /q1 q1 /q0 q0 v ddo 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 v ddo q7 /q7 q8 /q8 q9 /q9 v ddo v dd clk_sel clk0 /clk0 v bb (nc) clk1 /clk1 v ee q3 /q3 q4 /q4 q5 /q5 q6 /q6 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer with 2 to 1 diferential clock input mux p i 6 c 4911510 pi6c4911510 rev h 6/25/2015 15-0077
2 control input function table clk_sel outputs 0 clk0 1 clk1 pin description (1) pin # name ty pe description 1 v dd power core power supply 2 clk_sel input clock select input. when high, selects clk1 input. when low, selects clk0 input. lvcmos/lvttl level with 50k? pull down. 3 clk0 input diferential clock input with pull-down 4 /clk0 input inverting diferential clock input. defaults to v dd /2 if lef foating. 5 v bb (nc) power internal common mode voltage, can be lef as not connected if unused. 6 clk1 input diferential clock input with pull-down 7 /clk1 input inverting diferential clock input. defaults to v dd /2 if lef foating. 8 v ee power connect to negative power supply 9, 16, 25, 32 v ddo power output power pin 11, 10 q9, / q9 output diferential output pair, lvpecl interface level. 13,12 q8, / q8 output diferential output pair, lvpecl interface level. 15,14 q7, / q7 output diferential output pair, lvpecl interface level. 18,17 q6, / q6 output diferential output pair, lvpecl interface level. 20,19 q5, / q5 output diferential output pair, lvpecl interface level. 22,21 q4, / q4 output diferential output pair, lvpecl interface level. 24, 23 q3, / q3 output diferential output pair, lvpecl interface level. 27, 26 q2, / q2 output diferential output pair, lvpecl interface level. 29,28 q1, / q1 output diferential output pair, lvpecl interface level. 31,30 q0, / q0 output diferential output pair, lvpecl interface level. note: 1. i = input, o = output, p = power supply connection. pi6c4911510 rev h 6/25/2015 p i 6 c 4911510 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ 2 to 1 diferential clock input mux 15-0077
3 absolute maximum ratings (1) symbol parameter conditions min ty p max units v dd supply voltage referenced to gnd 4.6 v v in input voltage referenced to gnd -0.5 v dd +0.5v v i out surge current 100 ma t stg storage temperature -55 150 o c v bb sink/source current, i bb -0.5 +0.5 ma t j junction temperature 125 o c note: 1. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these ratings are stress specifca - tions only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifcations is not implied. exposure to absolute maximum rating conditions for extended periods may af fect product reliability. operating conditions symbol parameter conditions min ty p max units v dd core power supply voltage 2.375 3.6 v v ddo output power supply voltage 2.375 3.6 v t a ambient temperature -40 85 o c i dd core power supply current 70 95 ma i ddo output power supply current all lvpecl outputs unloaded 110 200 lvcmos/lvttl dc characteristics (ta = -40 o c to +85 o c, vdd = 3.3v 10%, vddo = 2.5v 5% to 3.3v 10%) symbol parameter conditions min ty p max units v ih input high voltage clk_sel 1.7 v dd +0.3 v v il input low voltage clk_sel -0.3 i ih input high current clk_sel v in = v dd = 3.6v 150 a i il input low current clk_sel v in = 0v, v dd = 3.6v -150 a r input pullup/pulldown resistance 50 k? pi6c4911510 rev h 6/25/2015 p i 6 c 4911510 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ 2 to 1 diferential clock input mux 15-0077
4 ac characteristics (t a = -40 o c to +85 o c, v dd = 3.3v 10%, v ddo = 2.5v 5% to 3.3v 10%) symbol parameter conditions min ty p max units f max output frequency 1500 mhz t pd propagation delay (1) 1200 ps tsk output-to-output skew (2) 40 ps t r /t f output rise/fall time 20% - 80% 150 ps t odc output duty cycle f 650 mhz 48 52 % v pp output swing lvpecl outputs 0.6 1.0 v t j bufer additive jitter rms 156.25mhz (12khz- 20mhz integration range) input condition per phase noise and additive jitter plot below 0.03 0.05 ps notes: 1. measured from the diferential input to the diferential output crossing point 2. defned as skew between outputs at the same supply voltage and with equal loads. measured at the output diferential crossing point lvpecl dc characteristics ( t a = -40 o c to +85 o c, v dd = 3.3v 10%, v ddo = 2.5v 5% to 3.3v 10%) symbol parameter conditions min ty p max units i ih input high current clk0, clk1 v in = v dd = 3.6v 150 a /clk0, /clk1 v in = v dd = 3.6v 150 a i il input low cur - rent clk0, clk1 v dd = 3.6v, v in = 0v -150 a /clk0, /clk1 v dd = 3.6v, v in = 0v -150 a v cmr common mode input voltage (1) v ee +0.5 v dd v v oh output high voltage (2) v ddo = 2.5v or 3.3v v ddo - 1.5 v ddo -1.4 v ddo -0.9 v v ol output low voltage (2) v ddo = 2.5v or 3.3v v ddo - 2.2 v ddo -2.0 v ddo -1.7 v r input pullup/pulldown resistance 50 k? notes: 1. for single-ended applications, the maximum input voltage for clk and /clk is v dd +0.3v 2. outputs terminated with 50 to v dd -2.0v pi6c4911510 rev h 6/25/2015 p i 6 c 4911510 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ 2 to 1 diferential clock input mux 15-0077
5 phase noise and additive jitter output phase noise (dark blue) vs input phase noise (light blue) additive jitter is calculated at ~27fs rms (12khz to 20mhz). additive jitter = (output jitter 2 - input jitter 2 ) confguration test load board termination for lvpecl outputs 100 z = 50 o z = 50 o 150 150 lvpec l buff er v ddqx l = 0 ~ 10 in. pi6c4911510 rev h 6/25/2015 p i 6 c 4911510 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ 2 to 1 diferential clock input mux 15-0077
6 application information wiring the differential input to accept single ended levels figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to postion the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r1/r2 = 0.609. figure 1. single-ended input to dif ferential input device single ended clock input v dd r1 1k r2 1k c1 0.1 clk /clk power supply filtering techniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor - mance, power supply isolation is required. all power pins should be individually connected to the power supply plane through vias, and 0.1f an 1f bypass capacitors should be used for each pin. v dd 0.1f 0.1f 1f v dd v ddo 1f v ddo pi6c4911510 rev h 6/25/2015 p i 6 c 4911510 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ 2 to 1 diferential clock input mux 15-0077
7 packaging mechanical: 32-pin qfn (zh) date: 06/30/11 description: 32-contact, thin quad flat no-lead (tqfn) package code: zh32 document control #: pd-2070 revision: b notes: 1. all dimensions are in mm. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals. 3. refer jedec mo-220 4. recommended land pattern is for reference only. 5. thermal pad soldering area (mesh stencile design is recommended) 11-0147 thermal information symbol description condition ja junction-to-ambient thermal resistance still air 44.70 c/w jc junction-to-case thermal resistance 21.70 c/w pi6c4911510 rev h 6/25/2015 p i 6 c 4911510 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ 2 to 1 diferential clock input mux 15-0077
8 packaging mechanical: 32-pin tqfp (fa) 1 seating plane 0.80 bsc .032 0.30 0.45 .012 .018 1.20 .047 0.95 1.05 .037 .041 x.xx x.xx denotes dimensions in millimeters 9.00 bsc .276 square 7.00 bsc .354 square gauge plane 1.00 ref .039 0.45 0.75 .018 .030 0.09 0.20 .004 .008 0 7 0.25 mm max. 0.10 .004 0.05 0.15 .002 .006 description: 32-pin, thin quad flat package, tqfp package code: fa document control no. pd - 1814 revision: c date: 03/09/05 pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 1-800-435-2335 ? www.pericom.com notes: 1. controlling dimensions in millimeters 2. ref.: jedec ms-026d/aba 3. package outline exclusive of mold flash and metal burr thermal information symbol description condition ja junction-to-ambient thermal resistance still air f&: jc junction-to-case thermal resistance &: pi6c4911510 rev h 6/25/2015 p i 6 c 4911510 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ 2 to 1 diferential clock input mux 15-0077
9 packaging mechanical: 32-pin tqfp with e-pad (fae) date: 03/24/15 description: 32 -pin, tqfp, 7x7, exposed pad package code: fae (fae32) document control #: pd-2196 revision: -- notes: 1.ref: jedec ms-026 aba-hd e1 c a1 a2 32 25 24 17 16 8 1 e a b e 1.20 max. 0.15 1.05 0.45 0.20 0.75 0.80 bsc min. 0.05 0.95 0.30 a a1 a2 b 0.09 0.45 e d1 d c e1 d2 l e symbols 8.75 9.25 6.90 7.10 7.10 9.25 6.90 8.75 3.90 3.19 1 8 16 9 24 17 32 25 d2 e2 l 7 0 e2 3.90 3.19 pkg. dimensions(mm) top view bottom view pin1 index area - side view d d1 15-0023 thermal information symbol description condition , ja junction-to-ambient thermal resistance still air 45 c/w jc junction-to-case thermal resistance 15 c/w pi6c4911510 rev h 6/25/2015 p i 6 c 4911510 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ 2 to 1 diferential clock input mux 15-0077
10 pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com ordering information (1,2,3) ordering code package code package description pi6c4911510zhie zh pb-free & green, 32-pin qfn pi6c4911510zhiex zh pb-free & green, 32-pin qfn, tape & reel pi6c4911510faie fa pb-free & green, 32-pin tqfp pi6c4911510faiex fa pb-free & green, 32-pin tqfp, tape & reel PI6C4911510FAEIE fae pb-free & green, 32-pin tqfp e-pad PI6C4911510FAEIEx fae pb-free & green, 32-pin tqfp e-pad, tape & reel notes: 1. t hermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = pb -free & green 3. x s uffx = tape/reel pi6c4911510 rev h 6/25/2015 p i 6 c 4911510 2.5v/3.3v 1.5ghz low skew 1-to-10 diferential to lvpecl fanout bufer w/ 2 to 1 diferential clock input mux 15-0077
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